Many modern high performance systems have multiple processors, many of which run independently but ultimately share one large common memory pool. Each processor typically has a small amount of fast local Random Access Memory (RAM). A large memory pool including Dynamic Random Access Memory (DRAM) (as well as Synchronous Dynamic Random Access Memory (SDRAM)) is usually shared amongst most or all the processors within a system.
DRAM bandwidth is very limited. Further, the access time of DRAMs is very slow, much slower than the bandwidth required for a single Central Processing Unit (CPU) let alone two or more CPUs. In large systems where four or eight CPU's are all trying to access the DRAM, arbitration must be carefully managed.
Complications to any arbitration scheme include situations where not all CPUs need to have the same priority. In particular, some CPUs may be allowed a greater share of the available bandwidth. For instance, in a two CPU system, one CPU may be performing mundane functions while the other CPU may be running time critical applications. In this case, it is preferable that the CPU running critical applications is allowed all the bandwidth it requires and only the bandwidth left over is given to the less important CPU.
Typical solutions to this problem have involved assigning a static priority to each CPU. For example, an arbiter will grant DRAM access to whichever requesting CPU has the highest priority.
FIG. 1 is an example of a system implementing a static priority scheme. As shown in FIG. 1, CPU A has the highest priority and the CPU C has the lowest priority. If all CPU's request access to DRAM (or SDRAM) at the same time, CPU A will be given access. If only CPU B and CPU C request access to SDRAM, then access is given to CPU B. CPU C only is given access if both CPU A or B do not require access to the shared resource.
Other arbitration schemes may include round robin, where priority is rotated, or a fixed tiered priority scheme. FIG. 2 is an example of a system implementing a round robin priority scheme. In a system of a plurality of CPUs (e.g., 3 CPUs) using a round robin priority scheme, whenever a CPU has been granted access to a bus, the priority associated with that CPU is reset to the lowest priority and the CPU which previously has the second highest priority will be promoted to the highest priority. In other words, if a CPU is granted access to the bus, that CPU goes to the back of the queue. Thus, priorities will change when a CPU has been granted access to the bus, with the granted CPU being assigned the lowest priority and the others being promoted up the priority ladder.
FIG. 3 is an example of a system implementing a fixed tiered priority scheme. In a fixed tiered priority scheme, CPU A and CPU B round robin between themselves but have priority over CPU C and CPU D which round robin between themselves.
However, current systems implementing fixed priority schemes have several drawbacks. As the number of CPUs in a system increases it has an unfortunate effect of ruthlessly punishing low priority CPUs. For example, if a system has four CPUs, it becomes increasingly unlikely that all of the three top highest CPUs are not requesting access to the SDRAM and thus giving the lowest priority CPU access. In addition, although a CPU may be assigned a low priority, the CPU may still have a maximum latency requirement. For instance, a CPU in a system may have the task of servicing a Universal Asynchronous Receiver Transmitter (UART). Although the UART may not need prompt servicing (due to internal First In First Out (FIFO) buffering), it may require servicing eventually otherwise the FIFO will fill up and data will be lost.
Therefore, there is a need for a more efficient method and system for efficiently allocating bandwidth (e.g., memory bandwidth) as well as other shared resources.